Reduction of power dissipation in sequential circuits
نویسندگان
چکیده
منابع مشابه
Reduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...
متن کاملReduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...
متن کاملSources of Power Dissipation in Cmos Circuits
The study of the power dissipation sources of CMOS circuits is presented. Specifically, the main principles of dynamic, short-circuit, static, and leakage power dissipation are illustrated together with the low power strategies for reducing each power component. Furthermore, we enlighten to some innovative techniques of power reduction, which are based on multiple supply voltages and multiple t...
متن کاملReduction of Static Power Dissipation in Adiabatic Combinational Circuits Using Power Gating MTCMOS
This paper proposes a method to reduce static power consumption in Adiabatic logic circuits based on Complementary Pass transistor Adiabatic Logic (CPAL) operated by two phase power clocks. We are applying power gating MTCMOS technique to reduce static power consumption in CPAL circuits. We tested MTCMOS power gating technique on 4-bit ripple carry adder to observe effect of static power reduct...
متن کاملMinimisation of Power Dissipation During Test Application in Full Scan Sequential Circuits Using Primary Input Freezing
This paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector u...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2008
ISSN: 0974-6846,0974-5645
DOI: 10.17485/ijst/2008/v1i3/10